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8737ag-11 www.icst.com/products/hiperclocks.html rev. a july 13, 2001 1

ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator g eneral d escription the ICS8737-11 is a low skew, high performance differential-to-3.3v lvpecl clock generator/ divider and a member of the hiperclocks? family of high performance clock solutions from ics. the ICS8737-11 has two selectable clock inputs. the clk, nclk pair can accept most standard differ- ential input levels. the pclk, npclk pair can accept lvpecl, cml, or sstl input levels.the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ICS8737-11 ideal for clock distribution applications demanding well defined performance and repeatability. f eatures ? 2 divide by 1 differential 3.3v lvpecl outputs; 2 divide by 2 differential 3.3v lvpecl outputs ? selectable clk, nclk or lvpecl clock inputs ? clk, nclk pair can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? pclk, npclk supports the following input types: lvpecl, cml, sstl ? maximum output frequency up to 650mhz ? translates any single ended input signal (lvcmos, lvttl, gtl) to lvpecl levels with resistor bias on nclk input ? output skew: 60ps (maximum) ? part-to-part skew: 200ps (maximum) ? bank skew: bank a - 20ps (maximum), bank b - 35ps (maximum) ? propagation delay: 1.7ns (maximum) ? 3.3v operating supply ? 0c to 70c ambient operating temperature ? industrial temperature information available upon request b lock d iagram p in a ssignment ICS8737-11 20-lead tssop 6.50mm x 4.40mm x 0.92 package body g package top view v ee clk_en clk_sel clk nclk pclk npclk nc mr v cc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 qa0 nqa0 v cc qa1 nqa1 qb0 nqb0 v cc qb1 nqb1 hiperclocks ? ,&6 qa0 nqa0 qa1 nqa1 1 2 d q le clk_en clk nclk pclk npclk mr qb0 nqb0 qb1 nqb1 clk_sel 0 1
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator t able 2. p in c haracteristics t able 1. p in d escriptions l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i k l c n , k l c 4f p k l c p n , k l c p 4f p , l e s _ k l c r m , n e _ k l c 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k w r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k w r e b m u ne m a ne p y tn o i t p i r c s e d 1v e e r e w o p. d n u o r g o t t c e n n o c . n i p y l p p u s e v i t a g e n 2n e _ k l cr e w o pp u l l u p . t u p n i k c o l c w o l l o f s t u p t u o k c o l c , h g i h n e h w . e l b a n e k c o l c g n i z i n o r h c n y s . h g i h d e c r o f e r a s t u p t u o q n , w o l d e c r o f e r a s t u p t u o q , w o l n e h w . s l e v e l e c a f r e t n i s o m c v l / l t t v l 3l e s _ k l ct u p n in w o d l l u p . s t u p n i k l c p n , k l c p s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i s o m c v l / l t t v l . s t u p n i k l c n , k l c s t c e l e s , w o l n e h w 4k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 5k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 6k l c pt u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 7k l c p nt u p n ip u l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i 8c nd e s u n u. t c e n n o c o n 9r mt u p n in w o d l l u p. r e d i v i d t u p t u o e h t s t e s e r . t e s e r r e t s a m 8 1 , 3 1 , 0 1v c c r e w o p. v 3 . 3 o t t c e n n o c . s n i p y l p p u s e v i t i s o p 2 1 , 1 11 b q , 1 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 1 , 4 10 b q , 0 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 1 , 6 11 a q , 1 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 10 a q , 0 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able s t u p n is t u p t u o r mn e _ k l cl e s _ k l ce c r u o s d e t c e l e s1 a q u r h t 0 a q1 a q n u r h t 0 a q n1 b q u r h t 0 b q1 b q n u r h t 0 b q n 1x x x w o lh g i hw o lh g i h 00 0 k l c n , k l cw o l ; d e l b a s i dh g i h ; d e l b a s i dw o l ; d e l b a s i dh g i h ; d e l b a s i d 00 1 k l c p n , k l c pw o l ; d e l b a s i dh g i h ; d e l b a s i dw o l ; d e l b a s i dh g i h ; d e l b a s i d 01 0 k l c n , k l cd e l b a n ed e l b a n ed e l b a n ed e l b a n e 01 1 k l c p n , k l c pd e l b a n ed e l b a n ed e l b a n ed e l b a n e e g d e k c o l c t u p n i g n i l l a f d n a g n i s i r a g n i w o l l o f d e l b a n e r o d e l b a s i d e r a s t u p t u o k c o l c e h t , s e h c t i w s n e _ k l c r e t f a . 1 e r u g i f f i n w o h s s a d e b i r c s e d s a s t u p n i k l c p n , k l c p d n a k l c n , k l c e h t f o n o i t c n u f a e r a s t u p t u o e h t f o e t a t s e h t , e d o m e v i t c a e h t n i . b 3 e l b a t n i s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p k l c p r o k l ck l c p n r o k l c nx a qx a q nx b qx b q n 00w o lh g i hw o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 11h g i hw o lh g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o lh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o lh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i o t t u p n i l a i t n e r e f f i d g n i r i w s e s s u c s i d h c i h w , 9 e r u g i f , 8 e g a p n o n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n . s l e v e l d e d n e e l g n i s t p e c c a enabled disabled f igure 1: clk_en t iming d iagram nclk, npclk clk, pclk clk_en nqa0 - nqa1, nqb0 - nqb1 qa0 - qa1, qb0 - qb1
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o -0.5v to v cc + 0.5v package thermal impedance, ja 73.2 c/w (0lfpm) storage temperature, t stg -65 c to 150 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in th e dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v5%, t a = 0 c to 70 c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v5%, t a = 0 c to 70 c t able 4c. d ifferential dc c haracteristics , v cc = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 5a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i r m , l e s _ k l c , n e _ k l c25 6 7 . 3v v l i r m , l e s _ k l c , n e _ k l c 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i n e _ k l cv n i v = c c v 5 6 4 . 3 =5a r m , l e s _ k l cv n i v = c c v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i n e _ k l cv n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a r m , l e s _ k l cv n i v , v 0 = c c v 5 6 4 . 3 =5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c nv n i v = c c v 5 6 4 . 3 =5a k l cv n i v = c c v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a k l cv n i v , v 0 = c c v 5 6 4 . 3 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 0 +v c c 5 8 . 0 -v s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n , v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t c c . v 3 . 0 + s i e g a t l o v e d o m n o m m o c : 2 e t o nv s a d e n i f e d h i .
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator t able 5. ac c haracteristics , v cc = 3.3v5%, t a = 0 c to 70 c t able 4d. lvpecl dc c haracteristics , v cc = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o m u m i x a m 0 5 6z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p k l c n , k l c ? z h m 0 5 6 3 . 17 . 1s n k l c p n , k l c p2 . 16 . 1 t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 6s p t ) b ( k s4 e t o n ; w e k s k n a b a k n a b0 2s p b k n a b5 3 t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 2s p t r e m i t e s i r t u p t u oz h m 0 5 @ % 0 8 o t % 0 20 0 30 0 7s p t f e m i t l l a f t u p t u oz h m 0 5 @ % 0 8 o t % 0 20 0 30 0 7s p c d oe l c y c y t u d t u p t u o 8 40 52 5% . e s i w r e h t o d e t o n s s e l n u z h m 0 0 5 t a d e r u s a e m s r e t e m a r a p l l a . r e t t i j d d a t o n s e o d t r a p e h t . t u p t u o e h t n o r e t t i j e h t l a u q e l l i w t u p n i e h t n o r e t t i j e l c y c - o t - e l c y c e h t . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i v n i v = c c v 5 6 4 . 3 =0 5 1a v n i v = c c v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i v n i v , v 0 = c c v 5 6 4 . 3 =5 -a v n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 3 . 01v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 1 +v c c v v h o 3 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 0 . 1 -v v l o 3 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 5 6 . 09 . 0v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + 0 5 h t i w d e t a n i m r e t s t u p t u o : 3 e t o n w v o t c c . v 2 -
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator t sk(o) qx nqx qy nqy p arameter m easurement i nformation f igure 2 - o utput l oad t est c ircuit scope qx nqx lvpecl v cc = 2.0v v cc f igure 4 - o utput s kew f igure 3 - d ifferential i nput l evel v cmr cross points v pp clk, pclk nclk, npclk v ee v cc v ee = -1.3v 0.135v
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator f igure 6 - i nput and o utput r ise and f all t ime clock inputs and outputs 20% 80% 20% 80% t r t f v swing f igure 8 - odc & t p eriod pulse width t period t pw t period odc = clk, pclk nclk, npclk f igure 5 - p art - to -p art s kew qx nqx qy nqy part 1 part 2 t sk(pp) f igure 7 - p ropagation d elay t pd nclk, npclk q0a0, q0a1 - q0b0, q0b1 nq0a0, nq0a1 - nq0b0, nq0b1 clk, pclk
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator application information wiring the differential input to accept single ended levels figure 9 shows how the differential input can be wired to accept single end levels. the reference voltage v_ref ~ v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 12.5v and v cc = 3.3v, v_ref should be 1.25v and r2/ r1 = 0.609. r2 1k v cc clk_in + - r1 1k c1 0.1uf v_ref f igure 9 - s ingle e nded s ignal d riving d ifferential i nput
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS8737-11. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS8737-11 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i cc_max = 3.465v * 50ma = 173.25mw ? power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 4 * 30.2mw = 120.8mw total power _max (3.465v, with all outputs switching) = 173.25mw + 120.8mw = 294.05mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125 c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used . assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6 c/w per table 6 below. therefore, tj for an ambient temperature of 70 c with all outputs switching is: 70 c + 0.294w * 66.6 c/w = 89.58 c. this is well below the limit of 125 c this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5 c/w 98.0 c/w 88.0 c/w multi-layer pcb, jedec standard test boards 73.2 c/w 66.6 c/w 63.5 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. table 6. thermal resistance ja for 20-pin tssop, forced convection
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 10. to calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) for logic high, v out = v oh_max = v cc_max ? 1.0v using v cc_max = 3.465, this results in v oh_max = 2.465v for logic low, v out = v ol_max = v cc_ma x ? 1.7v using v cc_max = 3.465, this results in v ol_max = 1.765v pd_h = [(2.465v - (3.465v - 2v))/50 ? ] * (3.465v - 2.465v) = 20.0mw pd_l = [(1.765v - (3.465v - 2v))/50 ? ] * (3.465v - 1.765v) = 10.2mw otal power dissipation per output pair = pd_h + pd_l = 30.2mw f igure 10 - lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator r eliability i nformation t ransistor c ount the transistor count for ICS8737-11 is: 510 t able 7. vs . a ir f low t able ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5 c/w 98.0 c/w 88.0 c/w multi-layer pcb, jedec standard test boards 73.2 c/w 66.6 c/w 63.5 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
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ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator p ackage o utline - g s uffix t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m n i mx a m n0 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 4 . 60 6 . 6 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 a 0 8 a a a- -0 1 . 0
8737ag-11 www.icst.com/products/hiperclocks.html rev. a july 13, 2001 13

ICS8737-11 l ow s kew 1/ 2 d ifferential - to - 3.3v lvpecl c lock g enerator t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 1 1 - g a 7 3 7 8 s c i1 1 - g a 7 3 7 8 s c ip o s s t d a e l 0 22 7c 0 7 o t c 0 t 1 1 - g a 7 3 7 8 s c i1 1 - g a 7 3 7 8 s c il e e r d n a e p a t n o p o s s t d a e l 0 20 0 5 2c 0 7 o t c 0

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